1. Field of the Invention
The invention relates in general to a memory control system and a memory control method, and more particularly to a memory control system and a memory control method capable of optimizing the memory usage performance.
2. Description of the Related Art
When data are written to or read from a memory, many steps including activating, instruction writing/reading and pre-charging have to be sequentially performed so that the data can be accessed. The request instructions for different sources have different methods for accessing the memory. In a display controller of a television system, for example, the display controller is for displaying video frames, and the display request instructions thereof shown in FIG. 1 correspond to the line-by-line data access to the memory. The data accessed according to the display request instructions for the line-by-line access in the memory are continuous, so the data access may be a pipeline access to achieve the best memory bandwidth availability.
In addition, taking the video decoder as an example, its decoding request instructions are shown in FIG. 2 and correspond to the block data access to the memory. However, the decoding request instructions corresponding to the block access may have the phenomenon that the page address is not hit but the bank address is hit when the memory addresses are switched. Thus, the pipeline method cannot be adopted to hide the activating instructions, thereby decreasing the performance, and the best memory bandwidth availability cannot be achieved. Thus, a tiling mechanism is disclosed. In the tiling mechanism, the memory addresses are mapped again so that the addresses of the data of the memory accessed by the video decoder are continuous although the memory is accessed with the block serving as one unit. Thus, the condition that the page address is not hit can be significantly reduced, and the memory bandwidth availability can be enhanced.
However, the television system available in the market usually contains a display controller and a video decoder. That is, two memory access methods including the line-by-line access and the block access do exist in the single system. Consequently, if the line-by-line access is adopted, then the memory accessing performance of the video decoder becomes poor. If the tiling mechanism is adopted to map the memory addresses again, then the memory accessing performance of the display controller becomes poor. That is, in the conventional memory access technology, the system including two memory access methods cannot achieve the best memory bandwidth availability.